The present invention relates to a composite MOS transistor device, including at least a pair of MOS transistors, for a semiconductor integrated circuit, and also relates to an operational amplifier as an exemplary embodiment of the composite MOS transistor device including the MOS transistor pair.
FIG. 10 illustrates a mask layout for a conventional MOS transistor pair. As shown in FIG. 10, a first MOS transistor M1 is paired with a second MOS transistor M2. The first MOS transistor M1 includes gate G1, source S and drain D1. Similarly, the second MOS transistor M2 also includes gate G2, source S and drain D2. The MOS transistor pair shown in FIG. 10 is applicable to a pair of differential transistors shown in FIG. 6 and a pair of current mirror transistors shown in FIG. 7, for example. In FIGS. 6 and 7, B denotes a board. In the pair of differential transistors or current mirror transistors, the source is connected in common because of the circuit configuration thereof. Accordingly, as in a mask layout shown in FIG. 11, a single source may be shared between the first and second MOS transistors M1 and M2 of FIG. 10. FIG. 12 illustrates an example where the gate width of each of the first and second MOS transistors M1 and M2 is divided into three and where the divided transistors are arranged in parallel to each other in the gate longitudinal direction. As shown in FIG. 12, the first MOS transistor M1 is constructed from three divided transistors M1a, M1b and M1c, each of which includes gate G1, source S and drain D1. The divided transistor M1b, located at the center, shares its drain and source with the drain of the divided transistor M1a and the source of the divided transistor M1c, respectively, on the right- and left-hand sides thereof. Similarly, the second MOS transistor M2 is also constructed from three divided transistors M2a, M2b and M2c, each of which includes gate G2, source S and drain D2. The divided transistor M2b, located at the center, shares its source and drain with the source of the divided transistor M2a and the drain of the divided transistor M2c, respectively, on the left- and right-hand sides thereof.
Conventional MOS transistor pairs of another type for semiconductor integrated circuit are disclosed, for example, in Japanese Laid-Open Publications Nos. 4-73961 and 5-90516. In the MOS transistor pair of this type, two pairs of transistors M1a & M1b and M2a & M2b, formed by dividing the gate width of each of first and second MOS transistors into two, are arranged diagonally, i.e., symmetrically about a point, as shown in FIG. 13.
A conventional MOS transistor pair of still another type is disclosed , for example, in Japanese Laid-Open Publication No. 2-12929. In the MOS transistor pair, two groups of transistors M1a through M1e and M2a through M2e, formed by dividing each of first and second MOS transistors into five, are arranged regularly and alternately as shown in FIG. 14.
In constructing a differential amplifier or a current mirror circuit from a pair of MOS transistors for a semiconductor integrated circuit, high current gain should be obtained while maintaining an adequate balance in output current.
However, in a conventional MOS transistor pair of any of these types, current flowing through a first MOS transistor may be greatly different from that flowing through a second MOS transistor or has low current gain. Hereinafter, this drawback will be described i n greater detail.
In general, a current value of an MOS transistor is given by EQU Id=k.multidot.W(Vgs-Vth).sup.2 /(2.multidot.L)
where Id is drain current of the MOS transistor, k is a current amplification factor of the transistor, W is the gate width of the transistor, Vgs is a gate-to-source voltage, Vth is the threshold voltage of the transistor and L is the gate length of the transistor.
The current balance between the first and second MOS transistors M1 and M2 in each of the MOS transistor pairs shown in FIGS. 10 and 11 will be considered. Since these MOS transistors M1 and M2 are not located at the same position on a chip, respective gate sizes of one of these transistors M1 and M2 may be different from those of the other because of various factors during the manufacturing process thereof. Herein, the width W and length L of the gate of the first MOS transistor M1 are supposed to be standard ones, and the respective differences in width and length between the first and second MOS transistors M1 and M2 are denoted by DW and DL, respectively. In such a case, the drain current Id of the second MOS transistor M2 is given by EQU Id=k.multidot.W(1+DW/W)(Vgs-Vth).sup.2 /{2.multidot.L(1+DL/L)}
Next, according to first-order approximation with DW/W and DL/L both supposed to be smaller than 1, the difference DId in drain current Id between the first and second MOS transistors M1 and M2 is given by EQU DId=Id(DW/W-DL/L)
This current difference leads to deterioration in performance of a circuit and decrease in yield of a semiconductor integrated circuit. In order to avoid such a situation, the MOS transistor pairs shown in FIGS. 10 and 11 are designed to have respective gate widths W and lengths L of large sizes. However, if the gate length L of an MOS transistor is increased, then the current can be amplified less by the transistor. Nevertheless, if the gate width W is further increased to compensate for such a low amplification factor, then the MOS transistor pair occupies a larger area on a semiconductor integrated circuit.
In the MOS transistor pair shown in FIG. 12, only the gate width W thereof is designed at a large size. However, the current difference between both transistors, resulting from the difference in gate length L, cannot be eliminated. In this case, the current difference between the two transistors M1 and M2 of the MOS transistor pair shown in FIG. 12 can be calculated as follows. The size precision of an MOS transistor in the gate longitudinal direction is approximately proportional to the distance from the centerline X-X' shown in FIG. 12. Each transistor is herein divided into three. Thus, supposing the difference in gate length in a region closer to the centerline X-X' is denoted by DL and the current value of each divided transistor is denoted by Idd, the current difference DId between these MOS transistors M1 and M2 is given by the sum of currents of the three equally divided transistors: EQU DId=Idd[{(DL+2DL+3DL)-(-DL-2DL-3DL)}/L]=Id(12DL/L)/3=4Id.multidot.DL/L
Thus, the current difference is large.
Similarly, the current difference between the two transistors cannot become zero in the MOS transistor pair shown in FIG. 14, either. In this. case, the current difference between these two transistors can be calculated as follows. Each transistor is herein divided into five. Thus, the current difference DId between these MOS transistors M1 and M2 is given by EQU DId=Idd[{(-4.5DL-0.5DL-1.5DL+2.5DL+3.5DL)-(4.5DL+1.5DL+0.5DL-2.5DL-3.5DL)}/ L]=-Id(DL/L)/5=-Id/5.multidot.DL/L
Thus, the current difference does not become zero, either.
In the MOS transistor pair shown in FIG. 13, the transistors are arranged symmetrically about a point, and an adequate balance can be advantageously maintained between currents. However, since the gate length L is longer than usual, the current cannot be amplified satisfactorily. In addition, two pairs of divided transistors are arranged diagonally. Accordingly, if an interconnect, connecting together the gates of one pair of divided transistors M1a and M1b, is routed preferentially, then the interconnect, connecting together the gates of the other pair of divided transistors M2a and M2b, should be routed so as not to overlap with the former interconnect. As a result, the routing process is adversely complicated and the total area occupied by these interconnects increases. In order to avoid such a situation, two interconnection layers should be provided.